Other Professional Activities

Reviews

Journals
- Microelectronics Journal, Elsevier (Outstanding Reviewer)
- Transactions on Very Large Scale Integration (TVLSI) Systems, IEEE
- Transactions on Dependable and Secure Computing (TDSC), IEEE
- Consumer Electronics Magazine, IEEE (10×)
- Security and Communication Networks, Hindawi - Wiley
- Microelectronic Engineering, Elsevier
- Cryptography, MDPI
- Journal of Industrial Information Integration, Elsevier
- Transactions on Circuits and Systems II: Express Briefs, IEEE
- Information, MDPI
- Transactions on Circuits and Systems I: Regular Papers, IEEE
- Discover Internet of Things, Springer
- Computation, MDPI
- Microprocessors and Microsystems, Elsevier
- Transactions on Information Forensics and Security, IEEE

Conferences, Workshops & Symposia
- International Symposium on Circuits and Systems (ISCAS) 2019, IEEE
- 2nd International Conference on Computer Applications & Information Security (ICCAIS 2019), IEEE Region 8
- 10th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2019), IACR
- International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2019, ACM & IEEE
- 4th IEEE International Circuit and System Symposium (ICSyS 2019), IEEE
- 15th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), IEEE
- 7th International Symposium on Security in Computing and Communications (SSCC 2019), Indian Institute of Information Technology and Management – Kerala (IIITM–K)
- International Symposium on Circuits and Systems (ISCAS) 2020, IEEE
- 3rd International Conference on Computer Applications & Information Security (ICCAIS 2020), IEEE Region 8
- IEEE Cloud Summit 2020, IEEE
- International Symposium on Circuits and Systems (ISCAS) 2021, IEEE

Presentations

Azure Meetup Berlin: Advanced Analytics for Highly Secured Environments: "Hardware-Entangled Security: Extracting a Secure Key from IoT Hardware", 9 November 2016, Berlin, Germany. [slides]
CROSSING Research Seminar: P3: "Hardware-Entangled Cryptography", 13 August 2015, Darmstadt, Germany. [slides]

Moderator

"Security of Cyber-Physical Systems" Session of the IEEE Computer Society DVP-SYP (Distinguished Visitors Program - Student & Young Professional) Virtual Conference on Hot Topics in Cybersecurity, 16-17 October 2020, online.
[IEEE website][on24 website]

Session Chair

Automotive 1 session, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin (ICCE-Berlin), 2-5 September 2018, Berlin, Germany.

Valet de Cyber

23rd ACM Conference on Computer and Communications Security (CCS 2016), 24-28 October 2016, Vienna, Austria.

Research Assistant (in Scientific Projects)

DFG Collaborative Research Centre (CRC) 1119: "CROSSING – Cryptography-Based Security Solutions: Enabling Trust in New and Next Generation Computing Environments"
- Project P3: Hardware-entangled security (Phase I: 2014-2018)
  In its Phase I, Project P3 concerned hardware-entangled cryptography, with a specific focus on Physical Unclonable Functions (PUFs). PUFs are hardware-based primitives used to establish security and trust with minimal hardware requirements. Therefore, PUFs can provide a trust anchor in the next-generation cloud and edge computing paradigm of highly distributed and heterogeneous networks of collaborative resource-limited embedded devices. Additionally, in the last decade before the start of CROSSING's Phase I, remarkable efforts had been put into developing novel PUF constructions and investigating their resilience to different kinds of attacks.
  In this project, we significantly advanced the state of the art in the scientific field of PUFs. More specifically, Project P3 was subdivided into three work packages, concerning: 1) the development of a comprehensive security framework for PUFs, 2) the design of PUF-based pseudorandom functions and 3) the development and evaluation of novel PUF constructions and practical PUF-based protocols.
  Project Website: https://www.crossing.tu-darmstadt.de
DFG Priority Program (SchwerPunktProgramme (SPP) 2253): "Nano Security: From Nano-Electronics to Secure Systems"
- Project NANOSEC: Tamper-Evident PUFs based on Nanostructures for Secure and Robust Hardware Security Primitives (Phase I: 2020-2023)
  In recent years, pronounced trends like the Internet of Things or 5G has led to more and more connected and digitalized cyber-physical systems. This results in an increased demand on embedded dedicated hardware security. Hence, unclonable, unpredictable and tamper-evident hardware security primitives, such as Physical Unclonable Functions (PUFs), became more and more important, since any software-only security solution can easily be defeated in case an attacker has full access to the device.
  In this tandem-project, we will investigate the suitability of nanomaterial-based devices such as Carbon Nanotube based field-effect transistors (CNT-FETs) for hardware security primitives featuring high entropy and robustness along with inherent tamper-evidence capabilities. Going beyond state of the art, we investigate important security characteristics like error correction, reliability, and tamper-evidence mechanisms of CNT-based PUFs. These investigations will induce novel insights regarding the applicability of such PUFs for forthcoming system integration technologies and in the emerging field of flexible/wearable electronics. We will cover technological developments for CNT-based PUFs and investigate different device designs which internalize multibit functionality as well as tamper-evidence. The realized PUFs will be subjected to an in-depth analysis exposing suitable error correction models to enable the extraction of stable PUF responses.
  Project Website: https://spp-nanosecurity.uni-stuttgart.de/
- PUFMem: Intrinsic Physical Unclonable Functions from Emerging Non-Volatile Memories (Phase I: 2020-2023)
  Recent developments have led to the proliferation of resource-constrained devices that undertake increasingly extensive and decisive tasks. Based on physical process variations during semiconductor manufacturing, memory-based physical unclonable functions (PUFs) provide lightweight, cost-efficient, and flexible hardware-based security primitives to protect these devices. Concurrently with these trends, the integration density of circuits is approaching the so-called scaling limit, where structures become so small that the saved information is hard to retrieve and that consequently brings novel non-volatile memory (NVM) types to the scene.
  In this project, we investigate the realization of intrinsic PUFs on commercially available NVMs. All obtained PUF instances will be systematically characterized according to established quality metrics. As PUFs from conventional memories are susceptible to varying temperature and supply voltage as well as magnetic fields and radiation, different environmental conditions for the characterization of PUF instances on NVMs will be created. In the next step, we will quantify the results and apply advanced techniques such as protocols, error-correcting codes, stochastic models etc. to improve PUF quality and resilience to influences from the environment. In particular, when used as random access memory in present-day computers, credentials and results of cryptographic operations are directly accessible on NVMs due to their inherent storage properties. We plan to overcome this drawback by employing self-encryption, where the same NVM is used for 2 different purposes: as a memory to store data and as a PUF for retrieving the key to encrypt this data.
  Project Website: https://spp-nanosecurity.uni-stuttgart.de/