Other Professional Activities

Reviews

  • Journals

    • Microelectronics Journal, Elsevier (Outstanding Reviewer)
    • Transactions on Very Large Scale Integration (TVLSI) Systems, IEEE
    • Transactions on Dependable and Secure Computing (TDSC), IEEE
    • Consumer Electronics Magazine, IEEE (10×)
    • Security and Communication Networks, Hindawi - Wiley
    • Microelectronic Engineering, Elsevier
    • Cryptography, MDPI
    • Journal of Industrial Information Integration, Elsevier
    • Transactions on Circuits and Systems II: Express Briefs, IEEE
    • Information, MDPI
    • Transactions on Circuits and Systems I: Regular Papers, IEEE
    • Discover Internet of Things, Springer
    • Computation, MDPI
    • Microprocessors and Microsystems, Elsevier
    • Transactions on Information Forensics and Security, IEEE
    • Computer Standards & Interfaces, Elsevier
    • Electronics, MDPI
    • Artificial Intelligence Review, Elsevier
    • Energy Reports, Elsevier
    • Micromachines, MDPI
    • Entropy, MDPI
    • Journal of Low-Power Electronics and Applications, MDPI
    • Sensors, MDPI
    • Frontiers in Signal Processing, Frontiers Media
    • Symmetry, MDPI
    • Transactions on Cognitive Communications and Networking, IEEE
    • Applied Sciences, MDPI
    • Future Internet, MDPI
  • Conferences, Workshops & Symposia

    • International Symposium on Circuits and Systems (ISCAS) 2019, IEEE
    • 2nd International Conference on Computer Applications & Information Security (ICCAIS 2019), IEEE Region 8
    • 10th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2019), IACR
    • International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2019, ACM & IEEE
    • 4th IEEE International Circuit and System Symposium (ICSyS 2019), IEEE
    • 15th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), IEEE
    • 7th International Symposium on Security in Computing and Communications (SSCC 2019), Indian Institute of Information Technology and Management Kerala (IIITMK)
    • International Symposium on Circuits and Systems (ISCAS) 2020, IEEE
    • 3rd International Conference on Computer Applications & Information Security (ICCAIS 2020), IEEE Region 8
    • IEEE Cloud Summit 2020, IEEE
    • International Symposium on Circuits and Systems (ISCAS) 2021, IEEE
    • 17th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2021), IEEE
    • 11th IEEE International Conference on Consumer [Electronics] Technology in Berlin (ICCE-Berlin 2021), IEEE
    • IEEE Cloud Summit 2021, IEEE
    • Design, Automation and Test in Europe (DATE) Conference 2022, European Design and Automation Association (EDAA) & IEEE
    • International Symposium on Circuits and Systems (ISCAS) 2022, IEEE
    • 12th IEEE International Conference on Consumer [Electronics] Technology in Berlin (ICCE-Berlin 2022), IEEE
    • IEEE Cloud Summit 2022, IEEE

Presentations

Moderator

  • "Security of Cyber-Physical Systems" Session of the IEEE Computer Society DVP-SYP (Distinguished Visitors Program - Student & Young Professional) Virtual Conference on Hot Topics in Cybersecurity, 16-17 October 2020, online.
    [IEEE website][on24 website]

Session Chair

Valet de Cyber

  • 23rd ACM Conference on Computer and Communications Security (CCS 2016), 24-28 October 2016, Vienna, Austria.

Research Assistant (in Scientific Projects)

  • NATO Security through Science: Information and Communication Security – Euro-Atlantic Partnership – Collaborative Linkage Grant (ICS.EAP.CLG) 983334: "Cryptography Using Chaotic Oscillators"
    • Bachelor's thesis student (2008-2010)
      This NATO Grant concerned the design, testing, and optimisation of non-linear digital circuits utilised for chaos-based communication and the study of their synchronisation under both optimal and noisy conditions. The latter topic formed the main subject discussed and examined in my bachelor's thesis, as well as the main issue addressed in my first publication.
  • DFG Collaborative Research Centre (CRC) 1119: "CROSSING – Cryptography-Based Security Solutions: Enabling Trust in New and Next Generation Computing Environments"
    • Project "P3: Hardware-Entangled Security" (Phase I: 2014-2018)
      In its Phase I, Project P3 concerned hardware-entangled cryptography, with a specific focus on Physical Unclonable Functions (PUFs). PUFs are hardware-based primitives used to establish security and trust with minimal hardware requirements. Therefore, PUFs can provide a trust anchor in the next-generation cloud and edge computing paradigm of highly distributed and heterogeneous networks of collaborative resource-limited embedded devices. Additionally, in the last decade before the start of CROSSING's Phase I, remarkable efforts had been put into developing novel PUF constructions and investigating their resilience to different kinds of attacks.
      In this project, we significantly advanced the state of the art in the scientific field of PUFs. More specifically, Project P3 was subdivided into three work packages, concerning: 1) the development of a comprehensive security framework for PUFs, 2) the design of PUF-based pseudorandom functions and 3) the development and evaluation of novel PUF constructions and practical PUF-based protocols.
  • DFG Priority Program (SchwerPunktProgramme (SPP)) 2253: "Nano Security: From Nano-Electronics to Secure Systems"
    • Project "NANOSEC: Tamper-Evident PUFs based on Nanostructures for Secure and Robust Hardware Security Primitives" (Phase I: 2020-2023)
      In recent years, pronounced trends like the Internet of Things or 5G has led to more and more connected and digitalized cyber-physical systems. This results in an increased demand on embedded dedicated hardware security. Hence, unclonable, unpredictable and tamper-evident hardware security primitives, such as Physical Unclonable Functions (PUFs), became more and more important, since any software-only security solution can easily be defeated in case an attacker has full access to the device.
      In this tandem-project, we will investigate the suitability of nanomaterial-based devices such as Carbon Nanotube based field-effect transistors (CNT-FETs) for hardware security primitives featuring high entropy and robustness along with inherent tamper-evidence capabilities. Going beyond state of the art, we investigate important security characteristics like error correction, reliability, and tamper-evidence mechanisms of CNT-based PUFs. These investigations will induce novel insights regarding the applicability of such PUFs for forthcoming system integration technologies and in the emerging field of flexible/wearable electronics. We will cover technological developments for CNT-based PUFs and investigate different device designs which internalize multibit functionality as well as tamper-evidence. The realized PUFs will be subjected to an in-depth analysis exposing suitable error correction models to enable the extraction of stable PUF responses.
    • Project "PUFMem: Intrinsic Physical Unclonable Functions from Emerging Non-Volatile Memories" (Phase I: 2020-2023)
      Recent developments have led to the proliferation of resource-constrained devices that undertake increasingly extensive and decisive tasks. Based on physical process variations during semiconductor manufacturing, memory-based physical unclonable functions (PUFs) provide lightweight, cost-efficient, and flexible hardware-based security primitives to protect these devices. Concurrently with these trends, the integration density of circuits is approaching the so-called scaling limit, where structures become so small that the saved information is hard to retrieve and that consequently brings novel non-volatile memory (NVM) types to the scene.
      In this project, we investigate the realization of intrinsic PUFs on commercially available NVMs. All obtained PUF instances will be systematically characterized according to established quality metrics. As PUFs from conventional memories are susceptible to varying temperature and supply voltage as well as magnetic fields and radiation, different environmental conditions for the characterization of PUF instances on NVMs will be created. In the next step, we will quantify the results and apply advanced techniques such as protocols, error-correcting codes, stochastic models etc. to improve PUF quality and resilience to influences from the environment. In particular, when used as random access memory in present-day computers, credentials and results of cryptographic operations are directly accessible on NVMs due to their inherent storage properties. We plan to overcome this drawback by employing self-encryption, where the same NVM is used for 2 different purposes: as a memory to store data and as a PUF for retrieving the key to encrypt this data.
    • Young Scientist Project "Chaos-Based Secure Communication"
      In the framework of this project, the implementation of circuits capable of chaotically encrypted, synchronised data transmission will be performed. Based on its inherent expertise in the relevant scientific field, our research team has already published a limited number of preliminary works. However, our research has considered only relatively simple chaotic implementations so far, i.e., the Chua chaotic circuit, and a measurement setup for carbon nanotube implementations.
      In this project, we propose to extend our collaborative research work both in the direction of more advanced security applications, with a focus on the potential use of such systems in the context of commercially available devices and products, as well as, towards the use of novel nanomaterials, e.g., memristors, or carbon nanotubes, for the implementation of the relevant chaotic circuits. In particular, we propose the following future contributions:
      • Characterisation of chaotic circuits based on commercially available novel nanomaterials, e.g., memristors.
      • Design and implementation of chaos-based systems for secure communication and other potentially more advanced security applications.
      • Experimental verification of the implemented devices, testing their robustness to environmental variations and noise.
      • Security evaluation and assessment, using attacker models suitable for the relevant commercial use cases, with an emphasis on a realistically acceptable level of security.